Recently, semiconductor devices having a configuration wherein multiple semiconductor elements are stacked together have been developed. For such semiconductor devices, there are existing methods to measure misalignment between the semiconductor elements which involve making and imaging an alignment mark on each semiconductor element. However, using these alignment marks, which are located internally of the edges of the chip of die, is difficult when multiple die or chips are stacked one above the other for the solder or other bonding of the chips together.
There remains a need for an inspection apparatus and method which can effectively and efficiently determine alignment quality between semiconductor elements being assembled into a stacked or laminated semiconductor device.